The present invention relates to a technique for restoring the normality of an electrically writable/erasable nonvolatile semiconductor memory, particularly a flash memory which is adapted to erase a certain number of bits of data at once, at the emergence of a memory cell having its threshold voltage falling below the prescribed level due to a cutoff of power supply or the like during the data writing or erasing operation.
A flash memory uses nonvolatile memory cells each formed of a MOSFET of the dual gate structure having a control gate and a floating gate. A memory cell stores a bit of data in terms of the shift of threshold voltage of MOSFET in response to the change of stored charges of the floating gate as shown in FIG. 16A. The state of high threshold voltage of MOSFET corresponds to data “1” and the state of low threshold voltage corresponds to data “0” in FIG. 16A.
Memory cells of this flash memory have their threshold voltage shifted by the data writing or erasing operation. Due to the disparity of memory cell characteristics, the threshold voltage shifts differently among memory cells, and there can emerge memory cells having their threshold voltage falling below 0 V (will be called “depletion state”) as shown by hatching in FIG. 16B. Usually, these memory cells in depletion state have their threshold voltage restored into the normal range based on the “write-up” or “write-back” operation.